HDL Logic Synthesis

Introduction to the syntax and elements of the basic VHDL language such as entities and architectures; creating combinational, synchronous logic and state machines using both structural and behavioral VHDL; using hierarchy in large designs; synthesizing and implementing designs. This course is dually listed with an equivalent undergraduate-level course (EE 440) and requires a minimum GPA of 2.75 or the instructor's permission for admission.

Credits

3 credits

Course Code

EE 540